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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">IFSR, Instruction Fault Status Register</h1><p>The IFSR characteristics are:</p><h2>Purpose</h2>
        <p>Holds status information about the last instruction fault.</p>
      <h2>Configuration</h2><p>AArch32 System register IFSR bits [31:0] are architecturally mapped to AArch64 System register <a href="AArch64-ifsr32_el2.html">IFSR32_EL2[31:0]</a>.</p><p>This register is present only when EL1 is capable of using AArch32. Otherwise, direct accesses to IFSR are <span class="arm-defined-word">UNDEFINED</span>.</p>
        <p>The current translation table format determines which format of the register is used.</p>
      <h2>Attributes</h2>
        <p>IFSR is a 32-bit register.</p>
      <h2>Field descriptions</h2><h3>When TTBCR.EAE == 0:</h3><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="15"><a href="#fieldset_0-31_17">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-16_16">FnV</a></td><td class="lr" colspan="3"><a href="#fieldset_0-15_13">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-12_12">ExT</a></td><td class="lr" colspan="1"><a href="#fieldset_0-11_11">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-10_10">FS[4]</a></td><td class="lr" colspan="1"><a href="#fieldset_0-9_9">LPAE</a></td><td class="lr" colspan="5"><a href="#fieldset_0-8_4">RES0</a></td><td class="lr" colspan="4"><a href="#fieldset_0-3_0">FS[3:0]</a></td></tr></tbody></table><h4 id="fieldset_0-31_17">Bits [31:17]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-16_16">FnV, bit [16]</h4><div class="field">
      <p>FAR not Valid, for a synchronous External abort other than a synchronous External abort on a translation table walk.</p>
    <table class="valuetable"><tr><th>FnV</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p><a href="AArch32-ifar.html">IFAR</a> is valid.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p><a href="AArch32-ifar.html">IFAR</a> is not valid, and holds an <span class="arm-defined-word">UNKNOWN</span> value.</p>
        </td></tr></table>
      <p>This field is valid only for a synchronous External abort other than a synchronous External abort on a translation table walk. It is <span class="arm-defined-word">RES0</span> for all other Prefetch Abort exceptions.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-15_13">Bits [15:13]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-12_12">ExT, bit [12]</h4><div class="field"><p>External abort type. This bit can be used to provide an <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> classification of External aborts.</p>
<p>In an implementation that does not provide any classification of External aborts, this bit is <span class="arm-defined-word">RES0</span>.</p>
<p>For aborts other than External aborts this bit always returns 0.</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-11_11">Bit [11]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-10_10">FS, bits [10, 3:0]</h4><div class="field">
      <p>Fault Status bits. Bits [10] and [3:0] are interpreted together.</p>
    <table class="valuetable"><tr><th>FS</th><th>Meaning</th><th>Applies when</th></tr><tr><td class="bitfield">0b00001</td><td>
          <p>PC alignment fault.</p>
        </td></tr><tr><td class="bitfield">0b00010</td><td>
          <p>Debug exception.</p>
        </td></tr><tr><td class="bitfield">0b00011</td><td>
          <p>Access flag fault, level 1.</p>
        </td></tr><tr><td class="bitfield">0b00101</td><td>
          <p>Translation fault, level 1.</p>
        </td></tr><tr><td class="bitfield">0b00110</td><td>
          <p>Access flag fault, level 2.</p>
        </td></tr><tr><td class="bitfield">0b00111</td><td>
          <p>Translation fault, level 2.</p>
        </td></tr><tr><td class="bitfield">0b01000</td><td>
          <p>Synchronous External abort, not on translation table walk.</p>
        </td></tr><tr><td class="bitfield">0b01001</td><td>
          <p>Domain fault, level 1.</p>
        </td></tr><tr><td class="bitfield">0b01011</td><td>
          <p>Domain fault, level 2.</p>
        </td></tr><tr><td class="bitfield">0b01100</td><td>
          <p>Synchronous External abort, on translation table walk, level 1.</p>
        </td></tr><tr><td class="bitfield">0b01101</td><td>
          <p>Permission fault, level 1.</p>
        </td></tr><tr><td class="bitfield">0b01110</td><td>
          <p>Synchronous External abort, on translation table walk, level 2.</p>
        </td></tr><tr><td class="bitfield">0b01111</td><td>
          <p>Permission fault, level 2.</p>
        </td></tr><tr><td class="bitfield">0b10000</td><td>
          <p>TLB conflict abort.</p>
        </td></tr><tr><td class="bitfield">0b10100</td><td>
          <p><span class="arm-defined-word">IMPLEMENTATION DEFINED</span> fault (Lockdown fault).</p>
        </td></tr><tr><td class="bitfield">0b11001</td><td>
          <p>Synchronous parity or ECC error on memory access, not on translation table walk.</p>
        </td><td>When FEAT_RAS is not implemented</td></tr><tr><td class="bitfield">0b11100</td><td>
          <p>Synchronous parity or ECC error on translation table walk, level 1.</p>
        </td><td>When FEAT_RAS is not implemented</td></tr><tr><td class="bitfield">0b11110</td><td>
          <p>Synchronous parity or ECC error on translation table walk, level 2.</p>
        </td><td>When FEAT_RAS is not implemented</td></tr></table><p>All other values are reserved.</p>
<p>For more information about the lookup level associated with a fault, see <span class="xref">'The level associated with MMU faults on a Short-descriptor translation table lookup'</span>.</p>
<p>The FS field is split as follows:</p>
<ul>
<li>FS[4] is IFSR[10].
</li><li>FS[3:0] is IFSR[3:0].
</li></ul><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-9_9">LPAE, bit [9]</h4><div class="field">
      <p>On taking a Data Abort exception, this bit is set as follows:</p>
    <table class="valuetable"><tr><th>LPAE</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Using the Short-descriptor translation table formats.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Using the Long-descriptor translation table formats.</p>
        </td></tr></table>
      <p>Hardware does not interpret this bit to determine the behavior of the memory system, and therefore software can set this bit to 0 or 1 without affecting operation.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-8_4">Bits [8:4]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h3>When TTBCR.EAE == 1:</h3><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="15"><a href="#fieldset_1-31_17">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_1-16_16">FnV</a></td><td class="lr" colspan="3"><a href="#fieldset_1-15_13">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_1-12_12">ExT</a></td><td class="lr" colspan="2"><a href="#fieldset_1-11_10">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_1-9_9">LPAE</a></td><td class="lr" colspan="3"><a href="#fieldset_1-8_6">RES0</a></td><td class="lr" colspan="6"><a href="#fieldset_1-5_0">STATUS</a></td></tr></tbody></table><h4 id="fieldset_1-31_17">Bits [31:17]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_1-16_16">FnV, bit [16]</h4><div class="field">
      <p>FAR not Valid, for a synchronous External abort other than a synchronous External abort on a translation table walk.</p>
    <table class="valuetable"><tr><th>FnV</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p><a href="AArch32-ifar.html">IFAR</a> is valid.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p><a href="AArch32-ifar.html">IFAR</a> is not valid, and holds an <span class="arm-defined-word">UNKNOWN</span> value.</p>
        </td></tr></table>
      <p>This field is valid only for a synchronous External abort other than a synchronous External abort on a translation table walk. It is <span class="arm-defined-word">RES0</span> for all other Prefetch Abort exceptions.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_1-15_13">Bits [15:13]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_1-12_12">ExT, bit [12]</h4><div class="field"><p>External abort type. This bit can be used to provide an <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> classification of External aborts.</p>
<p>In an implementation that does not provide any classification of External aborts, this bit is <span class="arm-defined-word">RES0</span>.</p>
<p>For aborts other than External aborts this bit always returns 0.</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_1-11_10">Bits [11:10]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_1-9_9">LPAE, bit [9]</h4><div class="field">
      <p>On taking a Data Abort exception, this bit is set as follows:</p>
    <table class="valuetable"><tr><th>LPAE</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Using the Short-descriptor translation table formats.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Using the Long-descriptor translation table formats.</p>
        </td></tr></table>
      <p>Hardware does not interpret this bit to determine the behavior of the memory system, and therefore software can set this bit to 0 or 1 without affecting operation.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_1-8_6">Bits [8:6]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_1-5_0">STATUS, bits [5:0]</h4><div class="field">
      <p>Fault status bits. Possible values of this field are:</p>
    <table class="valuetable"><tr><th>STATUS</th><th>Meaning</th><th>Applies when</th></tr><tr><td class="bitfield">0b000000</td><td>
          <p>Address size fault in translation table base register.</p>
        </td></tr><tr><td class="bitfield">0b000001</td><td>
          <p>Address size fault, level 1.</p>
        </td></tr><tr><td class="bitfield">0b000010</td><td>
          <p>Address size fault, level 2.</p>
        </td></tr><tr><td class="bitfield">0b000011</td><td>
          <p>Address size fault, level 3.</p>
        </td></tr><tr><td class="bitfield">0b000101</td><td>
          <p>Translation fault, level 1.</p>
        </td></tr><tr><td class="bitfield">0b000110</td><td>
          <p>Translation fault, level 2.</p>
        </td></tr><tr><td class="bitfield">0b000111</td><td>
          <p>Translation fault, level 3.</p>
        </td></tr><tr><td class="bitfield">0b001001</td><td>
          <p>Access flag fault, level 1.</p>
        </td></tr><tr><td class="bitfield">0b001010</td><td>
          <p>Access flag fault, level 2.</p>
        </td></tr><tr><td class="bitfield">0b001011</td><td>
          <p>Access flag fault, level 3.</p>
        </td></tr><tr><td class="bitfield">0b001101</td><td>
          <p>Permission fault, level 1.</p>
        </td></tr><tr><td class="bitfield">0b001110</td><td>
          <p>Permission fault, level 2.</p>
        </td></tr><tr><td class="bitfield">0b001111</td><td>
          <p>Permission fault, level 3.</p>
        </td></tr><tr><td class="bitfield">0b010000</td><td>
          <p>Synchronous External abort, not on translation table walk.</p>
        </td></tr><tr><td class="bitfield">0b010101</td><td>
          <p>Synchronous External abort on translation table walk, level 1.</p>
        </td></tr><tr><td class="bitfield">0b010110</td><td>
          <p>Synchronous External abort on translation table walk, level 2.</p>
        </td></tr><tr><td class="bitfield">0b010111</td><td>
          <p>Synchronous External abort on translation table walk, level 3.</p>
        </td></tr><tr><td class="bitfield">0b011000</td><td>
          <p>Synchronous parity or ECC error on memory access, not on translation table walk.</p>
        </td><td>When FEAT_RAS is not implemented</td></tr><tr><td class="bitfield">0b011101</td><td>
          <p>Synchronous parity or ECC error on memory access on translation table walk, level 1.</p>
        </td><td>When FEAT_RAS is not implemented</td></tr><tr><td class="bitfield">0b011110</td><td>
          <p>Synchronous parity or ECC error on memory access on translation table walk, level 2.</p>
        </td><td>When FEAT_RAS is not implemented</td></tr><tr><td class="bitfield">0b011111</td><td>
          <p>Synchronous parity or ECC error on memory access on translation table walk, level 3.</p>
        </td><td>When FEAT_RAS is not implemented</td></tr><tr><td class="bitfield">0b100001</td><td>
          <p>PC alignment fault.</p>
        </td></tr><tr><td class="bitfield">0b100010</td><td>
          <p>Debug exception.</p>
        </td></tr><tr><td class="bitfield">0b110000</td><td>
          <p>TLB conflict abort.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>When FEAT_RAS is implemented, <span class="binarynumber">0b011000</span>, <span class="binarynumber">0b011101</span>, <span class="binarynumber">0b011110</span>, and <span class="binarynumber">0b011111</span> are reserved.</p>
<p>For more information about the lookup level associated with a fault, see <span class="xref">'The level associated with MMU faults on a Long-descriptor translation table lookup'</span>.</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><div class="access_mechanisms"><h2>Accessing IFSR</h2><p>Accesses to this register use the following encodings in the System register encoding space:</p><h4 class="assembler">MRC{&lt;c&gt;}{&lt;q&gt;} &lt;coproc&gt;, {#}&lt;opc1&gt;, &lt;Rt&gt;, &lt;CRn&gt;, &lt;CRm&gt;{, {#}&lt;opc2&gt;}</h4><table class="access_instructions"><tr><th>coproc</th><th>opc1</th><th>CRn</th><th>CRm</th><th>opc2</th></tr><tr><td>0b1111</td><td>0b000</td><td>0b0101</td><td>0b0000</td><td>0b001</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HSTR_EL2.T5 == '1' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HSTR.T5 == '1' then
        AArch32.TakeHypTrapException(0x03);
    elsif EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HCR_EL2.TRVM == '1' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HCR.TRVM == '1' then
        AArch32.TakeHypTrapException(0x03);
    elsif HaveEL(EL3) &amp;&amp; ELUsingAArch32(EL3) then
        R[t] = IFSR_NS;
    else
        R[t] = IFSR;
elsif PSTATE.EL == EL2 then
    if HaveEL(EL3) &amp;&amp; ELUsingAArch32(EL3) then
        R[t] = IFSR_NS;
    else
        R[t] = IFSR;
elsif PSTATE.EL == EL3 then
    if SCR.NS == '0' then
        R[t] = IFSR_S;
    else
        R[t] = IFSR_NS;
                </p><h4 class="assembler">MCR{&lt;c&gt;}{&lt;q&gt;} &lt;coproc&gt;, {#}&lt;opc1&gt;, &lt;Rt&gt;, &lt;CRn&gt;, &lt;CRm&gt;{, {#}&lt;opc2&gt;}</h4><table class="access_instructions"><tr><th>coproc</th><th>opc1</th><th>CRn</th><th>CRm</th><th>opc2</th></tr><tr><td>0b1111</td><td>0b000</td><td>0b0101</td><td>0b0000</td><td>0b001</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HSTR_EL2.T5 == '1' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HSTR.T5 == '1' then
        AArch32.TakeHypTrapException(0x03);
    elsif EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HCR_EL2.TVM == '1' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HCR.TVM == '1' then
        AArch32.TakeHypTrapException(0x03);
    elsif HaveEL(EL3) &amp;&amp; ELUsingAArch32(EL3) then
        IFSR_NS = R[t];
    else
        IFSR = R[t];
elsif PSTATE.EL == EL2 then
    if HaveEL(EL3) &amp;&amp; ELUsingAArch32(EL3) then
        IFSR_NS = R[t];
    else
        IFSR = R[t];
elsif PSTATE.EL == EL3 then
    if SCR.NS == '0' then
        IFSR_S = R[t];
    else
        IFSR_NS = R[t];
                </p></div><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:05; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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